Title:    VLSI Building Blocks   (Poster)

Time: Thursday, March 18, 3:45 PM - 5:45 PM

Location:    Exhibit Hall E 3

Chair: John McCanny    (The Queenąs University of Belfast)

3:45 PM    DISPS 2.1
Hybrid Multiplier/CORDIC Unit for Online Handwriting Recognition
Stephen McInerney (DSP Group, Dept. of Electronic & Electrical Engineering, University College Dublin), Richard B Reilly (Dept. of Electronic & Electrical Engineering, University College Dublin)
[abstract]  [vol. 4, pp. 1909-1912]

DISPS 2.2
Low-Power Bit-Serial Viterbi Decoder for Next Generation Wide-Band CDMA Systems
Hiroshi Suzuki (Kawasaki Steel Corporation, LSI Division), Yun-Nan Chang, Keshab K Parhi (University of Minnesota, Minneapolis)
[abstract]  [vol. 4, pp. 1913-1916]

DISPS 2.3
A Highly-scalable Symmetric/Asymmetric FIR Processor
Wei-Lung Liu, Oscal T.-C. Chen, Heng-Chou Chen (National Chung Cheng University), Hsun-Chang Hsieh (Industrial Technology Research Institute)
[abstract]  [vol. 4, pp. 1917-1920]

DISPS 2.4
A NOVEL MEMORY-BASED FFT PROCESSOR FOR DMT/OFDM APPLICATIONS
Ching-Hsien Chang, Chin-Liang Wang, Yu-Tai Chang (Department of Electrical Engineering, National Tsing Hua University Hsinchu, Taiwan 300, Republic of China)
[abstract]  [vol. 4, pp. 1921-1924]

DISPS 2.5
Synthesis of Array Architectures for Block Matching Motion Estimation: Design Exploration using the tool DG2VHDL
John Bonk (Naval Systems, Electronic Design Laboratory , Raytheon), Andrew Stone, Elias S Manolakos (Communications and Digital Signal Processing (CDSP) Center for Research and Graduate Studies, Northeastern University)
[abstract]  [vol. 4, pp. 1925-1928]

DISPS 2.6
A High-Throughput, Low Power Architecture and Its VLSI Implementation for DFT/IDFT Computation
Wei-Ren Shiue, Shen-Fu Hsiao (Inst. Compt. Eng., NSYSU, Taiwan)
[abstract]  [vol. 4, pp. 1929-1932]

DISPS 2.7
NOVEL MAPPING OF A LINEAR QR ARCHITECTURE
LIGHTBODY GAYE (QUEEN'S UNIVERSITY BELFAST, NORTHERN IRELAND), RICHARD L WALKE (DEFENSE EVALUATION AND RESEARCH AGENCY, MALVERN, ENGLAND), ROGER F WOODS, JOHN V McCANNY (QUEEN'S UNIVERSITY BELFAST, NORTHERN IRELAND)
[abstract]  [vol. 4, pp. 1933-1936]

DISPS 2.8
An Unrestrictedly Parallel Scheme for Ultra-High-Rate Reprogrammable Huffman Coding
Robert A Freking, Keshab K Parhi (Dept. of Electrical and Computer Engineering, University of Minnesota)
[abstract]  [vol. 4, pp. 1937-1940]

DISPS 2.9
FLEXIBLE VIDEO COMPRESSION SYSTEMS USING AN ANALOG VECTOR QUANTIZATION CHIP
Stefano Rovetta, Rdolfo Zunino (DIBE - Genoa University)
[abstract]  [vol. 4, pp. 1941-1944]

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Last Update: 5:27 GMT, March 24, 1999 Ingo Höntsch